1. Field of the Invention
The present invention relates to a chemical mechanical polishing method. More particularly, the present invention relates to a chemical mechanical polishing method for polishing a silicon oxide layer.
2. Description of the Related Art
A multi-layer wiring structure may be employed in a semiconductor device if the semiconductor device is required to have a high capacity and a high degree of integration. The multi-layer wiring structure is generally formed by repeatedly performing processes for forming and patterning a conductive layer and an insulation layer. After the conductive layer and the insulation layer are etched to form a conductive layer pattern and an insulation layer pattern, planarization processes are carried out. Owing to the planarization processes, successive photolithography for forming the conductive layer pattern and the insulation layer pattern may be efficiently performed. The planarization processes may be typically divided into a local planarization process and a global planarization process. However, the ultimate goal of the planarization processes is to achieve the global planarization.
An etch-back process, a reflow process, and a chemical mechanical polishing process have been developed as planarization processes. The chemical mechanical polishing process is largely employed for forming a highly integrated circuit because the chemical mechanical polishing process efficiently achieves the global planarization of a layer to be polished. This is also because the chemical mechanical polishing process may efficiently achieve a relatively high planarity.
The chemical mechanical polishing process is developed by International Business Machines (IBM) Corp. in the late 1980s. In the chemical mechanical polishing process, a semiconductor substrate is disposed beneath a polishing head of a chemical mechanical polishing apparatus. A polishing pad is positioned under the semiconductor substrate. A slurry composition including deionized water, an abrasive and an additive is provided onto the semiconductor substrate. The semiconductor substrate and the polishing pad may be moved with respect to each other while the polishing pad makes contact with the semiconductor substrate. Thus, a surface portion of the semiconductor substrate may be planarized. The abrasive of the slurry composition and protrusions of the polishing pad may mechanically polish the surface portion of the semiconductor substrate. Simultaneously, the surface portion of the semiconductor substrate is chemically polished by reactions between chemical components included in the slurry composition and ingredients in the surface portion of the semiconductor substrate.
A polishing efficiency of the chemical mechanical polishing process may be determined by the chemical mechanical polishing apparatus, the slurry composition, and the type of the polishing pad. In particular, the efficiency of the chemical mechanical polishing process may be increased by selectively using at least two slurry compositions. For example, a conventional method selectively using at least two slurry compositions is disclosed in Korean Patent Laid-Open Publication No. 2001-0061124.
In addition, a high-planarity slurry chemical mechanical polishing (HPS-CMP) process using a high-planarity slurry composition capable of improving planarity has been developed.
The HPS-CMP process is characterized by a layer having a stepped portion that is passivated by polymers to reduce a chemical polishing rate of the layer. Thus, the layer may be mechanically polished from the stepped portion rather than chemically. When the stepped portion is removed, an area of the layer, the area contacting a polishing pad of a chemical mechanical polishing apparatus employed for performing the HPS-CMP process, may become wide. That is, the flat surface area increases. In addition, the area may also be passivated by the polymers. Because the layer is not chemically polished because of the polymers attached to the layer, the area of the layer may be substantially dense. Thus, the layer may hardly be polished either chemically or mechanically after the stepped portion is removed. That is, the HPS-CMP process may stop by itself after the stepped portion is removed. In other words, a self-stopping characteristic may appear. As a result, a substantially high planarity may be easily achieved by employing the HPS-CMP process.
However, although the HPS-CMP process is employed, if a substrate formed under the layer has a protrusion having an upper face, then the protrusion of the substrate may be partially removed in removing the stepped portion of the layer.
FIG. 1 is a cross-sectional view illustrating a substrate and a silicon oxide layer formed on the substrate before a conventional HPS-CMP process is performed on the silicon oxide layer. FIG. 2 is a cross-sectional view illustrating the substrate and the silicon oxide layer after the conventional HPS-CMP process is performed on the silicon oxide layer.
Referring to FIG. 1, a substrate 100 includes a first stepped portion 110 and a second stepped portion 120 connected to the first stepped portion 110. The first stepped portion 110 includes at least two patterns adjacent to each other. In addition, the first stepped portion 110 includes a first upper face 110a, a first lower face 110b positioned below the first upper face 110a and a first sidewall 110c between the first upper face 110a and the first lower face 110b. 
The first upper face 110a and the first lower face 110b may be substantially horizontal. In addition, the first upper face 110a may be substantially parallel with the first lower face 110b. The first sidewall 110c may be substantially vertical. In addition, the first sidewall 110c may be substantially perpendicular to the first upper face 110a and the first lower face 110b. 
The second stepped portion 120 may include a second upper face 120a, a second lower face 120b positioned below the second upper face 120a and a second sidewall 120c between the second upper face 120a and the second lower face 120b. 
The first lower face 110b of the first stepped portion 110 and the second upper face 120a of the second stepped portion 120 may be substantially coplanar. That is, the first lower face 110b may correspond to the second upper face 120a. Thus, the first stepped portion 110 may be to the second stepped portion 120.
A layer 200 is formed on the substrate 100 to cover the first and second stepped portions 110 and 120. The layer 200 has a third stepped portion positioned over the first upper face 110a of the first stepped portion 110. The third stepped portion may conform to the first stepped portion 110.
A portion 201 of a surface of the layer 200, the portion 201 being positioned directly over the lower face 120b of the second stepped portion 120, is positioned below a polishing target face 300 corresponding to the upper face 110a of the first stepped portion 110.
Referring to FIG. 2, the conventional HPS-CMP process using the high-planarity slurry composition is performed on the layer 200. Thus, the layer 200 is polished to the polishing target face 300. As illustrated in FIG. 2, the first and second stepped portions 110 and 120 of the substrate 100 are partially removed.
In performing the HPS-CMP process, a polishing pad positioned directly over the lower face 120b of the second stepped portion 120 may be positioned lower than the polishing pad positioned directly over the upper face 110a of the first stepped portion 110. Thus, although the first stepped portion 110 is removed, the HPS-CMP process may not stop by itself. That is, the self-stopping characteristic may not appear. Furthermore, corners of the first and second stepped portions 110 and 120 may be excessively polished because of an orbital movement of the polishing pad. Thus, the first and second stepped portions 110 and 120 may be unfortunately damaged.
As a result, a chemical mechanical polishing method capable of achieving a substantially high planarity as well as fully protecting a structure covered with a layer that is to be polished is an important topic of research.